The 8085 Microprocessor

Pending Interrupts or  Read Interrupt Mask (RIM) instruction Because there are several interrupt lines, when one interrupt request is being served other interrupt requests may occur and remain pending. The 8085 has an additional instruction called RIM (Read Interrupt Mask) to sense these pending interrupts.  Read Interrupt Mask (RIM) –  This instruction is used to read the status of the hardware interrupts (RST 7.5, RST 6.5, RST 5.5) by loading into the A register a byte which defines the condition of the mask bits for the interrupts. It also reads the condition of SID (Serial Input Data) bit on the microprocessor. Instruction RIM:- Read Interrupt Mask. The is a 1-byte instruction that can be used for the following functions. To read interrupt masks. This instruction loads the accumulator with 8 bits indicating the current status of the interrupt masks. To identify pending interrupts. Bits D4, D5 and D6 identify the pending interrupts. To receive serial data. Bit D7

Set Interrupt Mask (SIM) instruction Set Interrupt Mask (SIM) –  It is used to implement the hardware interrupts (RST 7.5, RST 6.5, RST 5.5) by setting various bits to form masks or generate output data via the Serial Output Data (SOD) line. First the required value is loaded in accumulator then SIM will take the bit pattern from it. Instruction SIM: Set Interrupt Mask. This is a 1-byte instruction and can be used for three different functions. one function is set mask for RST 7.5, RST 6.5 and RST 5.5 interrupts. This instruction reads the content of the accumulator and enables or disables the interrupts according to the content of the accumulator. Bit D3 is a control bit and should =1 for bit D0, D1 and D2 to be effective. Logic 0 on D0, D1, and D2 will enable the corresponding interrupts, and logic 1 will disable the interrupts. The second function is to reset RST 7.5 flip-flop. Bit D4 is additional control for RST 7.5. If D4=1, RST 7.5 reset. This is used to overrid

Table: Comparison between Memory Mapped I/O and I/O Mapped I/O S.No Memory Mapped I/O S.No I/O Mapped I/O 1 Address width is 16-bit. A0 to A15 are used to generate address of the device. 1 Address width is 8-bit. A0 to A15 lines are used to generate address of the device. 2 MEMR and MEMW control signals are used to control read and write I/O operations respectively. 2 IOR and IOW control signals are used to control read and write I/O operations respectively. 3 Instructions available are STA addr, LDA addr, LDAX rp, STAX rp, ADD M, CMP M, MOV r, M, etc. 3 IN and OUT are the only available instructions. 4 Data transfer takes place between any register and I/O device. 4 Data transfer takes place between accumulator and I/O device. 5 Maximum number of I/O devices that can be addressed is 65536 (theoretically). 5 Maximum num