Pin Configuration and Function of 8085
Pin Configuration and Function of 8085
Properties:-
• It is an 8-bit microprocessor
• Manufactured with N-MOS technology
• 40
pin IC package
• It
has 16-bit address bus and thus has 216 = 64 KB addressing capability.
•
Operate with 3 MHz single-phase clock • +5 V single power supply
The
logic pin layout and signal groups of the 8085microprocessor are shown in Fig.
All the signals are classified into six groups:
•
Address bus
• Data
bus
•
Control & status signals
•
Power supply and frequency signals
•
Externally initiated signals
•
Serial I/O signals
Figure: - The 8085 Microprocessor Pin Configuration and
Signals
The
Intel 8085A is a new generation, complete 8 bit parallel central processing
unit (CPU). The 8085A uses a multiplexed data bus. The address is split between
the 8bit address bus and the 8bit data bus. Figures are at the end of the
document.
Pin Description
The
following describes the function of each pin:
A6
- A1s (Output 3 State)
Address
Bus; The most significant 8 bits of the memory address or the 8 bits of the I/0
addresses, 3 stated during Hold and Halt modes.
AD0
- 7 (Input/Output 3state)
Multiplexed
Address/Data Bus; Lower 8 bits of the memory address (or I/0 addresses) appear
on the bus during the first clock cycle of a machine state. It then becomes the
data bus during the second and third clock cycles. 3 stated during Hold and
Halt modes.
ALE
(Output)
Address
Latch Enable: It occurs during the first clock cycle of a machine state and
enables the address to get latched into the on chip latch of peripherals. The
falling edge of ALE is set to guarantee setup and hold times for the address
information. ALE can also be used to strobe the status information. ALE is
never 3stated.
SO,
S1 (Output)
Data
Bus Status. Encoded status of the bus cycle:
S1 S0
0 0 HALT
0 1
WRITE
1 0
READ
1 1
FETCH
S1 can
be used as an advanced R/W status.
RD
(Output 3state) READ; indicates the selected memory or 1/0 device is to be read
and that the Data Bus is available for the data transfer. WR (Output 3state)
WRITE; indicates the data on the Data Bus is to be written into the selected
memory or 1/0 location. Data is set up at the trailing edge of WR. 3stated
during Hold and Halt modes.
Table :- 8085 machine cycle status and control signals
READY
(Input)
If
Ready is high during a read or write cycle, it indicates that the memory or
peripheral is ready to send or receive data. If Ready is low, the CPU will wait
for Ready to go high before completing the read or write cycle.
HOLD
(Input)
HOLD;
indicates that another Master is requesting the use of the Address and Data
Buses. The CPU, upon receiving the Hold request. Will relinquish the use of
buses as soon as the completion of the current machine cycle. Internal
processing can continue. The processor can regain the buses only after the Hold
is removed. When the Hold is acknowledged, the Address, Data, RD, WR, and IO/M
lines are 3stated.
HLDA
(Output)
HOLD
ACKNOWLEDGE; indicates that the CPU has received the Hold request and that it
will relinquish the buses in the next clock cycle. HLDA goes low after the Hold
request is removed. The CPU takes the buses one half clock cycle after HLDA
goes low.
INTR
(Input)
INTERRUPT
REQUEST; is used as a general purpose interrupt. It is sampled only during the
next to the last clock cycle of the instruction. If it is active, the Program
Counter (PC) will be inhibited from incrementing and an INTA will be issued.
During this cycle a RESTART or CALL instruction can be inserted to jump to the
interrupt service routine. The INTR is enabled and disabled by software. It is
disabled by Reset and immediately after an interrupt is accepted.
Table:-8085 interrupts and externally initiated signals
INTA
(Output)
INTERRUPT
ACKNOWLEDGE; is used instead of (and has the same timing as) RD during the
Instruction cycle after an INTR is accepted. It can be used to activate the
8259 Interrupt chip or some other interrupt port.
RST
5.5
RST
6.5 - (Inputs)
RST
7.5
RESTART INTERRUPTS; These three inputs have the same timing as I NTR except
they cause an internal RESTART to be automatically inserted.
RST
7.5 ~~ Highest Priority
RST
6.5
RST
5.5 o Lowest Priority
The
priority of these interrupts is ordered as shown above. These interrupts have a
higher priority than the INTR.
TRAP
(Input)
Trap
interrupt is a nonmaskable restart interrupt. It is recognized at the same time
as INTR. It is unaffected by any mask or Interrupt Enable. It has the highest
priority of any interrupt.
RESET
IN (Input)
Reset
sets the Program Counter to zero and resets the Interrupt Enable and HLDA flip-flops.
None of the other flags or registers (except the instruction register) are
affected The CPU is held in the reset condition as long as Reset is
applied.
RESET
OUT (Output)
Indicates
CPlJ is being reset. Can be used as a system RESET. The signal is synchronized
to the processor clock.
X1,
X2 (Input)
Crystal
or R/C network connections to set the internal clock generator X1 can also be
an external clock input instead of a crystal. The input frequency is divided by
2 to give the internal operating frequency.
CLK
(Output)
Clock
Output for use as a system clock when a crystal or R/ C network is used as an
input to the CPU. The period of CLK is twice the X1, X2 input period.
IO/M
(Output)
IO/M
indicates whether the Read/Write is to memory or l/O Tristated during Hold and
Halt modes.
SID
(Input)
Serial
input data line the data on this line is loaded into accumulator bit 7 whenever
a RIM instruction is executed.
SOD
(output)
Serial
output data line. The output SOD is set or reset as specified by the SIM
instruction.
Vcc
+5
volt supply.
Vss
Ground
Reference.
REFERENCES
- R. S. Gaonkar, Microprocessor
Architecture, Programming, and Applications with the 8085, Fifth Edition,
Penram International Publishing (India) Private Limited.
- S Ghoshal, Microprocessor Based
System Design, Macmillan India Limited, 1996
- M. Mano, Digital Logic and
Computer Design, Prentice – Hall India
- B.
Ram - Fundamentals of Microprocessor and Microcontrollers
- “Microprocessors: Principles
and Applications” by A Pal
- “Microprocessors and
Microcontrollers : Architecture, Programming and Interfacing Using 8085,
8086 and 8051” by Soumitra Kumar Mandal
- “Introduction to
Microprocessors and Microcontrollers” by Crisp John Crisp
- “Microprocessors And
Microcontrollers” by A Nagoor Kani
- “Microprocessors And
Microcontrollers : Architecture, Programming and System Design 8085, 8086,
8051, 8096” by KRISHNA KANT
- “8 - Bit
Microprocessor”
by Vibhute
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