Timing Diagrams of 8085
Timing Diagrams of 8085
To know the working of 8085 microprocessor, we should know the timing diagram
of 8085 microprocessor. With help of timing diagram we can easily calculate the
execution time of instruction as well as program. It is the graphical
representation of process in steps with respect to time. Before
go for timing diagram of 8085 microprocessor we should know some basic
parameters to draw timing diagram of 8085 microprocessor. Those parameters are
·
Instruction Cycle
·
Machine cycle
·
T-state.
1. Instruction cycle: this term is defined as
the number of steps required by the cpu to complete the entire process ie.
Fetching and execution of one instruction. The fetch and execute cycles are
carried out in synchronization with the clock.
Instruction
Cycle = Fetch Cycle (FC) + Execute Cycle (EC).
2. Machine cycle: It is the time required
by the microprocessor to complete the operation of accessing the memory devices
or I/O devices. In machine cycle various operations like opcode fetch, memory
read, memory write, I/O read, I/O write are performed.
3. T-state: Each clock cycle is
called as T-states. It is a basic unit used to calculate the time
taken for execution of instructions and programs in a processor.
·
Now let us discuss the timing diagram for various signals that are
associated with 8085 microprocessor.
IO/M’, S0, S1:
From the
previous discussions about 8085 microprocessor, we very well know that IO/M’,
S0, S1 are the status signals of the microprocessor. These status signals
decide the type of machine cycle is to be executed.
ALE (Address latch enable)
ALE is indicates the
availability of a valid address on the multiplexed address/data lines. When it
is high act as an address bus and low act as a data bus.
Rd^ (Read)
Read is an active low signal
that indicates that data is to be read form the selected memory or i/o device
through data bus.
WR^ (write)
Write is an active low signal
that indicates that data on the data bus is to be write form the selected
memory or i/o device.
Data Bus (D0-D7):
While dealing with data bus, two types of data flow are possible.
The data can be transferred from memory to microprocessor and vice versa.This
process occurs during the T2 and T3 states.
Lower byte address (A0-A7):
The lower byte of address is available on the time multiplexed
address/date bus during the T1 state of machine cycle, except the bus idle
machine cycle.
Higher byte addresses (A8-A15):
The higher byte addresses (A8-A15) is available for T1, T2 and T3
states of each machine cycle, except the bus idle machine cycle.
Timing
Diagram
Opcode fetch:
·
The microprocessor requires instructions to perform any particular
action. In order to perform these actions microprocessor utilizes Opcode which
is a part of an instruction which provides detail(ie. Which operation
microprocessor needs to perform) to microprocessor.
Fig: Opcode
fetch timing diagram
Read and write timing diagram for memory and I/O Operation
Memory Read :
Figure: Memory read timing diagram
Operation:
·
It is used to fetch one byte from the memory.
·
It requires 3 T-States.
·
It can be used to fetch operand or data from the memory.
·
During T1, A8-A15 contains higher byte of address. At the same
time ALE is high. Therefore Lower byte of address A0-A7 is selected from
AD0-AD7.
·
Since it is memory ready operation, IO/M(bar) goes low.
·
During T2 ALE goes low, RD(bar) goes low. Address is removed from
AD0-AD7 and data D0-D7 appears on AD0-AD7.
·
During T3, Data remains on AD0-AD7 till RD(bar) is at low signal.
Memory Write:
Figure: Memory write timing
diagram
Operation:
·
It is used to send one byte into memory.
·
It requires 3 T-States.
·
During T1, ALE is high and contains lower address A0-A7 from
AD0-AD7.
·
A8-A15 contains higher byte of address.
·
As it is memory operation, IO/M(bar) goes low.
·
During T2, ALE goes low, WR(bar) goes low and Address is removed
from AD0-AD7 and then data appears on AD0-AD7.
·
Data remains on AD0-AD7 till WR(bar) is low.
IO Read:
Figure: I/O read timing diagram
Operation:
·
It is used to fetch one byte from an IO port.
·
It requires 3 T-States.
·
During T1, The Lower Byte of IO address is
duplicated into higher order address bus A8-A15.
·
ALE is high and AD0-AD7 contains address of IO
device.
·
IO/M (bar) goes high as it is an IO operation.
·
During T2, ALE goes low, RD (bar) goes low and
data appears on AD0-AD7 as input from IO device.
·
During T3 Data remains on AD0-AD7 till RD(bar) is
low.
IO Write:
Figure:I/O write timing diagram
Operation:
·
It is used to writ one byte into IO device.
·
It requires 3 T-States.
·
During T1, the lower byte of address is duplicated into higher
order address bus A8-A15.
·
ALE is high and A0-A7 address is selected from AD0-AD7.
·
As it is an IO operation IO/M (bar) goes low.
·
During T2, ALE goes low, WR (bar) goes low and data appears on
AD0-AD7 to write data into IO device.
·
During T3, Data remains on AD0-AD7 till WR(bar) is low.
REFERENCES
- R. S. Gaonkar, Microprocessor Architecture, Programming, and Applications with the 8085, Fifth Edition, Penram International Publishing (India) Private Limited.
- S Ghoshal, Microprocessor Based System Design, Macmillan India Limited, 1996
- M. Mano, Digital Logic and Computer Design, Prentice – Hall India
- B. Ram - Fundamentals of Microprocessor and Microcontrollers
- “Microprocessors: Principles and Applications” by A Pal
- “Microprocessors and Microcontrollers : Architecture, Programming and Interfacing Using 8085, 8086 and 8051” by Soumitra Kumar Mandal
- “Introduction to Microprocessors and Microcontrollers” by Crisp John Crisp
- “Microprocessors And Microcontrollers” by A Nagoor Kani
- “Microprocessors And Microcontrollers : Architecture, Programming and System Design 8085, 8086, 8051, 8096” by KRISHNA KANT
- “8 - Bit Microprocessor” by Vibhute
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